Cadence Design Systems, Inc. announced a collaboration with Arm to deliver a chiplet-based reference design and software development platform to accelerate software-defined vehicle (SDV) innovation. The automotive reference design, initially for advanced driver assistance system (ADAS) applications, specifies a scalable chiplet architecture and interface interoperability to foster industry-wide collaboration, enable heterogeneous integration and expand system innovation. The solution is architected and built using the latest generation of Arm Automotive Enhanced technologies and Cadence IP.

The complementary software stack development platform is provided as a digital twin of the hardware that is compliant with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative software standard, enabling software development to begin before hardware is available and allowing subsequent system integration validation. The combined solution speeds both hardware and software development, accelerating time-to-market. The new solution architecture and reference design provide a standard for chiplet interface interoperability, addressing a critical industry need.

The Cadence components of the solution include: Helium Virtual and Hybrid Studio for the rapid creation of virtual and hybrid platforms and Helium Software Digital Twin to support deployment at scale for software developers I/O IP solutions for interface and memory protocols, including Universal Chiplet Interconnect Express (UCIe) for high-speed chiplet-to-chiplet communication Comprehensive compute IP portfolio including advanced AI solution, the Neo neural processing unit (NPU) IP, the NeuroWeave software development kit (SDK) for machine learning (ML) solutions, and world-class DSP compute solutions The virtual platform and component IP for the reference platform are available now for early adopters.